Performance estimation of flash analog-to-digital converter using resonant-tunneling MML/MOBILE logic gates

We have estimated the performance of a flash analog-to-digital converter (ADC) that consists of ternary quantizers and a ternary-to-binary encoder using resonant-tunneling diodes (RTDs). The ternary quantizers consist of resonant-tunneling monostable-to-multistable transition logic (MML) circuits, while the encorder consists of multiple-valued multiple -input monostable-to-bistable transition logic elements (M-MOBILEs). By assuming InP-based RTDs and heterojunction field-effect transistors (HFETs), we have carried out SPICE simulation that demonstrates a 4-bit, 10-GS/s ADC operation with a power dissipation of 0.23 W. The input bandwidth, which is defined as a frequency at which the effective number of bit decreases by 3 dB, was estimated to be 500 MHz.